CYT4DNJBJS datasheet(106/209 Pages) INFINEON

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Datasheet

106

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID66B

IDD_HIB3

VDDD current,

Hibernate Mode + RTC at

32.768 kHz

––

µA

TA = 85°C, using WCO,

VDDD = 5.5 V

SID66C

IDD_HIB4

VDDD current,

Hibernate Mode + RTC at

32.768 kHz

–

150

µA

TA = 25°C using LPECO

4 MHz, 20 pF load of LPECO

VDDD = 5.0 V

SID66D

IDD_HIB5

VDDD current,

Hibernate Mode + RTC at

32.768 kHz

–

215

µA

TA = 85°C, using LPECO

4 MHz, 20 pF load of LPECO

VDDD = 5.5 V

Power Mode Transition Times

SID69_1

tACT_DS

Power down time from ACTIVE to

DEEPSLEEP (using the internal

regulator)

––

2.8

µs

When IMO is already running

and all HFCLK roots are at

least 8 MHz. HFCLK roots

that are slower than this will

require additional time to

turn off.

SID69A

tACT_DS

Power down time from ACTIVE to

DeepSleep (using external PMIC)

––

6.5

µs

When IMO is already running

and all HFCLK roots are at

least 8MHz.HFCLK rootsthat

are slower than this will

require additional time to

turn off. The time for the

PMIC to deassert its power

good signal is not included.

SID67

tDS_ACT

DeepSleep to Active transition

time (IMO clock, flash execution)

––

µs

When using 8 MHz IMO.

Measured from wakeup

interrupt during DeepSleep

until Flash execution.

TA ≥ –5°C

Note: At temperatures below

–5°C the DeepSleep to Active

transition time can be higher

than the max time indicated by

as much as 20 µs

SID67A

tDS_ACT_FLL DeepSleep to Active transition

time (FLL clock, flash execution)

––

µs

When using FLL to generate

96 MHz from the 8-MHz IMO.

Measured from wakeup

interrupt during DeepSleep

until Flash execution.

TA ≥ –5°C

Note: At temperatures below

–5°C the DeepSleep to Active

transition time can be higher

than the max time indicated by

as much as 20 µs

SID67B

tDS_ACT_PLL DeepSleep to Active transition

time (PLL clock)

––

µs

When using PLL to generate

96 MHz from the 8-MHz IMO.

Measured from wakeup

interrupt during DeepSleep

until PLL locks.

TA ≥ –5°C

Note: At temperatures below

–5°C the DeepSleep to Active

transition time can be higher

than the max time indicated by

as much as 20 µs

Table 26-3

DC specifications, CPU current, and transition time specifications (continued)

All specifications are valid for –40°C  TA  105°C and for 2.7 V to 5.5 V except where noted.

Spec ID

Parameter

Description

Min

Typ Max Units

Details/conditions

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