MPC821 datasheet(215/242 Pages) NXP

215 / 242 page

Support Information

MOTOROLA

MPC860TFADS Daughter Board Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

PB18

I/O, X

MPC PI/O port B 18. Appears also at P8 but otherwise unused.

E_TENA

I/O, H

Ethernet port Transmit Enable. Connected to the SCC’s RTS~

signal. When active, transmit is enabled via the MC68160 EEST.

When the ethernet port is disabled via BCSR1, may be used off-

board for any alternate function.

GND

N.C.

ETHEN~

O, L

Ethernet Port Enable. Connected to BCSR1. See

TABLE 4-10.

“BCSR1 Description” on page 49. In the motherboard

documentations.

N.C.

IRD_EN~

O, L

Infra-Red Enable. Connected to BCSR1. See

TABLE 4-10.

“BCSR1 Description” on page 49.In the motherboard

documentations.

PA1

I/O, X

MPC PI/O port A 1. Appears also at P8 but otherwise unused.

GND

N.C.

PA0

I/O, X

MPC PI/O port A 0. Appears also at P8 but otherwise unused.

GND

TMS

I/O, X

JTAG port Test Mode Select input. Used to select test through the

JTAG port. Pulled-up but otherwise not used on the FADS.

PB16

I/O, X

MPC PI/O port B 16. Appears also at P8 but otherwise unused.

TRST~

O, L

JTAG port Reset. Pulled down with a zero ohm resistor, so that

the JTAG logic is constantly reset. Otherwise unused on the

FADS.

PB15

I/O, X

MPC PI/O port B 15. Appears also at P8 but otherwise unused.

RS_EN1~

O, L

RS232 port 1 Enable. Connected to BCSR1. See

TABLE 4-10.

“BCSR1 Description” on page 49. In the motherboard

documentations.

PB14

I/O, X

MPC PI/O port B 14. Appears also at P8 but otherwise unused.

PC4

I/O, X

MPC PI/O port C 4. Appears also at P8 but otherwise unused.

PC5

I/O, X

MPC PI/O port C 5. Appears also at P8 but otherwise unused.

100

PC6

I/O, X

MPC PI/O port C 6. Appears also at P8 but otherwise unused.

101

GND

TABLE 5-11. PM3 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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