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PDP83TG720SWCSTQ1 bảng dữ liệu(PDF) 157 Page - Texas Instruments

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PDP83TG720SWCSTQ1 bảng dữ liệu(HTML) 157 Page - Texas Instruments

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7.6.2.99 PMA_PMD_CONTROL_1 Register (Address = 0x1000) [reset = 0x0]
PMA_PMD_CONTROL_1 is shown in Table 7-122.
Return to the Summary Table.
Table 7-122. PMA_PMD_CONTROL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
pma_reset_2
R
1b0
1 = PMA/PMD reset 0 = Normal operation Note - RW bit, self
clearing Note - 0x1 added in [15:12] to differentiate
1b0 = Normal operation
1b1 = PMA/PMD reset
14-12
RESERVED
R
3b000
Reserved
11
cfg_low_power_2
R
1b0
1 = Low-power mode 0 = Normal operation Note - RW bit Note - 0x1
added in [15:12] to differentiate
1b0 = Normal operation
1b1 = Low-power mode
10-0
RESERVED
R
11b0000000
0000
Reserved
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DP83TG720S-Q1
SNLS604 – SEPTEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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