PDP83TG720SWCSTQ1 datasheet(64/199 Pages) TI

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7.6.2.8 MII_REG_12 Register (Address = 0x12) [reset = 0x0]

MII_REG_12 is shown in Table 7-31.

Return to the Summary Table.

Table 7-31. MII_REG_12 Register Field Descriptions

Bit

Field

Type

Reset

Description

link_qual_int

1b0

Link quality bad interrupt status

energy_det_int

1b0

Energy det change interrupt status

link_int

1b0

Link status change interrupt status

RESERVED

1b0

Reserved

esd_int

1b0

ESD fault detected interrupt status

ms_train_done_int

1b0

Training done interrupt status

RESERVED

1b0

Reserved

RESERVED

1b0

Reserved

link_qual_int_en

R/W

1b0

Link quality bad interrupt enable

energy_det_int_en

R/W

1b0

Energy det change interrupt enable

link_int_en

R/W

1b0

Link status change interrupt enable

unused_int_3

R/W

1b0

Reserved

esd_int_en

R/W

1b0

ESD fault detected interrupt enable

ms_train_done_int_en

R/W

1b0

Training done interrupt enable

unused_int_2

R/W

1b0

Reserved

unused_int_1

R/W

1b0

Reserved

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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