PDP83TG720SWCSTQ1 datasheet(13/199 Pages) TI

13 / 199 page

Over operating free-air temperature range (unless otherwise noted)(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDDIO Sensor Accuracy ( Voltage and

Temperature Variation)

-40

℃ to 125℃

15.4

VDDIO Sensor Accuracy Part-to-Part

-40

℃ to 125℃

15.4

(1)

Ensured by production test, characterization or design

(2)

For pins: MDC, INT, RESET, LED_1, STRP_1, RX_CTRL, CLKOUT, RX_D[3:0], RX_CLK, TX_CLK, TX_CTRL, TX_D[3:0], LED_0,

and MDIO

(3)

For pins: MDC, INT, RESET, LED_1, STRP_1, RX_CTRL, CLKOUT, RX_D0, RX_D1, RX_CLK, TX_CLK, TX_CTRL, TX_D2, TX_D3,

LED_0, and MDIO

(4)

For pins: TX_D0, TX_D1, RX_D2, and RX_D3

6.6 Timing Requirements

(1)

PARAMETER

TEST

CONDITIONS

MIN

NOM

MAX

UNIT

POWER-UP TIMING

T5.1

VDDA3P3 Duration(2)

0% to 100% (+/- 10

VDDA3P3)

0.5

T5.2

VDD1P0 Duration(2)

0% to 100% (+/- 10

VDD1P0)

0.1

T5.2

VDDIO Duration(2)

VDDIO = 1.8V

0.1

T5.2

VDDIO Duration(2)

VDDIO = 2.5V

0.1

T5.2

VDDIO Duration(2)

VDDIO = 3.3V

0.1

T5.2

VSLEEP Duration (2)

0% to 100% (+/- 10

VSLEEP)

0.1

T5.3

Crystal stabilization-time post power-up (from last power rail

ramp to 100%)

1500

µs

T5.4

Osillator stabilization-time post power-up ( from last power

rail ramp to 100%)(3)

T5.5

Post power-up stabilization-time prior to MDC preamble for

T5.6

Hardware configuration latch-in time from power-up

T5.7

Hardware configuration pins transition to functional mode from

latch-in completion

110

T5.8

PAM3 IDLE Stream from power-up (Master Mode)

RESET TIMING (RESET_N)

T6.1

RESET pulse width

µs

T6.2

Post reset stabilization-time prior to MDC preamble for register

access

T6.3

Hardware configuration latch-in time from reset

µs

T6.4

Hardware configuration pins transition to functional mode from

latch-in completion

1.5

µs

T6.5

PAM3 IDLE Stream from reset (Master Mode)

1500

µs

SMI TIMING

T4.1

MDC to MDIO (Output) Delay Time (25 pF load)

T4.2

MDIO (Input) to MDC Setup Time

T4.3

MDIO (Input) to MDC Hold Time

MDC Frequency ( 25 pF load)

2.5

MHz

RECEIVE LATENCY TIMING

SSD symbol on MDI to Rising edge of RGMII RX_CLK with

assertion of RX_CTRL

µs

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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