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PDP83TG720SWCSTQ1 bảng dữ liệu(PDF) 67 Page - Texas Instruments

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PDP83TG720SWCSTQ1 bảng dữ liệu(HTML) 67 Page - Texas Instruments

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7.6.2.11 MII_REG_18 Register (Address = 0x18) [reset = 0x8]
MII_REG_18 is shown in Table 7-34.
Return to the Summary Table.
Table 7-34. MII_REG_18 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ack_received_int
R
1b0
Ack received interrupt status (OAM)
14
tx_valid_clr_int
R
1b0
mr_tx_valid clear interrupt status (OAM)
13
link_state_ind_fall_bmw_i
nt
R
1b0
BMW interrupt status (see advanced features)
12
link_state_ind_rise_bmw_i
nt
R
1b0
BMW interrupt status(see advanced features)
11
por_done_int
R
1b0
POR done interrupt status
10
no_frame_int
R
1b0
No frame detect interrupt status
9
wake_req_int
R
1b0
Wake request interrupt status
8
lps_int
R
1b0
LPS interrupt status
7
ack_received_int_en
R/W
1b0
Ack received interrupt enable (OAM)
6
tx_valid_clr_int_en
R/W
1b0
mr_tx_valid clear interrupt enable (OAM)
5
link_state_ind_fall_bmw_i
nt_en
R/W
1b0
BMW interrupt (see advanced features)
4
link_state_ind_rise_bmw_i
nt_en
R/W
1b0
BMW interrupt (see advanced features)
3
por_done_int_en
R/W
1b1
POR done interrupt enable
2
no_frame_int_en
R/W
1b0
No frame detect interrupt enable
1
wake_req_int_en
R/W
1b0
Wake request interrupt enable
0
lps_int_en
R/W
1b0
LPS interrupt enable
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DP83TG720S-Q1
SNLS604 – SEPTEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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