PDP83TG720SWCSTQ1 datasheet(73/199 Pages) TI

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7.6.2.17 CLK_CTRL_CFG Register (Address = 0x182) [reset = 0x0]

CLK_CTRL_CFG is shown in Table 7-40.

Return to the Summary Table.

Table 7-40. CLK_CTRL_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

cfg_force_mas_mode_clk

_ctrl_val

R/W

1b0

Force value for master/slave control for clock control

cfg_force_mas_mode_clk

_ctrl_en

R/W

1b0

Force enable for master/slave control for clock control

cfg_200m_clk_sel_force_v

R/W

1b0

Force value for sys clock mux select

cfg_200m_clk_sel_force_e

R/W

1b0

Force enable for sys clock mux select

11-0

gate_clk_dis

R/W

12b0000000

00000

Allows the user to disable clock gating (keep clock/s enable). Every

bit, when set to one constantly enables one clock as specifies

bellow: Bit[11]: sgmii_clk Bit[10]: wol_clk Bit[9]: rgmii_clk Bit[8]:

rmii_clk Bit[7]: rx10_sf_clk Bit[6]: txg_sf_clk Bit[5]: reg_file_clk Bit[4]:

top_clk Bit[3]: an_clk Bit[2]: core_10m_clk Bit[1]: 100m_tx_clk Bit[0]:

100m_rx_clk, ce_a_clk

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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