PDP83TG720SWCSTQ1 datasheet(72/199 Pages) TI

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7.6.2.16 PM_TOP_CFG Register (Address = 0x181) [reset = 0x440]

PM_TOP_CFG is shown in Table 7-39.

Return to the Summary Table.

Table 7-39. PM_TOP_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

RESERVED

4b0000

Reserved

cfg_lps_xtal_pwrdn_en

R/W

1b0

cfg_lps_mac_pwrdn_en

R/W

1b1

Enable power down of mac inf during Low power mode

cfg_lps_pll_pwrdn_en

R/W

1b0

cfg_lps_dbg_mode

R/W

1b0

LPS debug mode enable to reduce the sleep request timeout

7-6

cfg_lps_slp_rqst_to

R/W

2b01

Sleep rquest timer threshold. 2'b00 = 0.4ms, 2'b01 = 1ms, 2'b10 =

4ms, 2'b11 = 16ms

5-4

ld_pwr_up_wait

R/W

2b00

Determine additional wait time between de-assertion reset to last

DDS to assertion of pwr_seq_done: 00: no additional wait 01: 1ms

10: 2ms 11: 4ms This value should deal with potential problem in

Line Driver power-up time.

pll_gf_reset_reg

R/W

1b0

1 = Reset is high 0 = Reset is low

force_pll_gf_reset

R/W

1b0

1 = Force pll_clk mux reset to value defined in bit[8] 0 = Normal

mode

pll_clk_sel_reg

R/W

1b0

1: select PLL clock 0: select REF clock

force_pll_ctrl

R/W

1b0

1: force pll_clk_mux selec to value defined in Bit[2] 0: Do not force

pll_clk_mux select (Normal)

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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