PDP83TG720SWCSTQ1 datasheet(4/199 Pages) TI

4 / 199 page

Pin Functions

STATE(1)

DESCRIPTION

NAME

NO.

MAC INTERFACE

RX_D3

RX_M

S, PD, O

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the

rising edge of RX_CLK. They contain valid data when RX_DV(decoded from RX_CTL) is asserted. A nibble,

RX_D[3:0], is transmitted in RGMII mode.

RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC.

RX_D2

RX_P

RX_D1

RX_D0

RX_CLK

Receive Clock: In RGMII mode, PHY provides this 125-MHz clock to MAC.

Unused in SGMII mode

RX_CTRL

S, PD, O

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a

single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of

RX_CLK.

Used only as strap in SGMII mode

TX_CLK

Transmit Clock: In RGMII mode, MAC provides this 125-MHz clock to PHY.

Unused in SGMII mode

TX_CTRL

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single

signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented on the falling edge of TX_CLK.

Unused in SGMII mode

TX_D3

Transmit Data: In RGMII mode, the transmit data nibble, TX_D[3:0], is received from the MAC .

TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.

TX_D2

TX_D1

TX_P

TX_D0

TX_M

SERIAL MANAGEMENT INTERFACE

MDC

Management Data Clock: Synchronous clock to the MDIO serial management input and output data.

MDIO

OD, IO

Management Data Input/Output: Bidirectional management data signal that may be sourced by the management

station or the PHY. This pin requires an external pull-up resistor (recommended value = 2.2-kΩ) .

CONTROL INTERFACE

INT

PU, OD, O

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak

internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set,

This pin can be configured as an Active-HIGH output using register[0x0011].

RESET

PU, I

RESET: Active-LOW input, which initializes or reinitializes the DP83TG720S-Q1. Asserting this pin LOW for at least

10 μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for

each bit in the Register Map section. All bootstrap pins are resampled upon deassertion of reset.

INH

PMOS OD

INH: Active-HIGH PMOS open-drain output. When the PHY enters the sleep state, PHY will release the INH pin to

allow an external pull-down resistor (recommended value = 10 kΩ) to pull the line to ground. When in any other

state, the INH pin will drive a HIGH state to the VSLEEP rail.

WAKE

PD, I

WAKE: Active-HIGH (this pin works on VSLEEP domain) pulse on wake-up pin wakes up the PHY from the sleep

state. For pulse width, refer to timing section. This pin can be directly tied to the VSLEEP rail when the sleep state

is not used or left float.

STRP_1

PD, I

Strap 1: This pin is for strapping PHY_AD bits.

CLOCK INTERFACE

Reference Clock Input: Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator input. The device

supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator

connected to pin XI only and XO left floating.

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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