PDP83TG720SWCSTQ1 datasheet(32/199 Pages) TI

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Table 7-3. Sensor Select Table (continued)

Sensor Selected To Read-out

0x4920

Temperature Sensor

Table 7-4. Sensor's Constant Values

Constant

Value (in decimal)

vdda_output_mean_code

128

slope_vdda3p3_sensor

8.63014e-3

vdd1p0_output_mean_code

slope_vdd1p0_sensor

2.85714e-3

vddio_output_mean_code

224

slope_vddio_sensor

15.686e-3

temperature_output_mean_code

161

slope_temperature_sensor

1.5

Note

Accuracy of temperature sensor can be maximized (3degreeC for temperature < 105C and 7.5

degreeC for temperature > 105C), if customer can sample "temperature_output_code" at 25C

and use it as "temperature_output_mean_code".

7.3.1.5 Electrostatic Discharge Sensing

Electrostatic discharge is a serious issue for electronic circuits and if not properly mitigated can create short-term

issues (signal integrity, link drops, packet loss) as well as long-term reliability faults. The DP83TG720S-Q1 has

robust integrated ESD circuitry and offers an ESD sensing architecture. ESD events can be detected on MDI

pins for further analysis and debug.

The ESD sensing tool is useful for both prototyping and end-applications. Additionally, the DP83TG720S-Q1

provides an interrupt status flag; when an ESD event is logged in the register<0x0442>. Hardware and software

resets are ignored by the ESDS register to prevent unwarranted clearing.

Table 7-5. ESD Sensing : Interrupt Setting and Count Reading

Function

Required Read/Write

Interrupt Enable

•

Write register<0x0012>[3] = 1

ESD Event Counter

•

Read register<0x0442>[14:9]

•

Value in decimal indicates the ESD strikes since power-up.

7.3.2 Compliance Test Modes

The six test modes for the DP83TG720S-Q1 are compliant to IEEE 802.3bp, Sub-clause 97.5.2. Supported test

modes allow testing of the transmitter waveform Power Spectral Density (PSD) mask, distortion, MDI Master

jitter, MDI Slave jitter, droop, transmitter frequency, frequency tolerance, BER monitoring, return loss, and mode

conversion. Any of the three GPIOs can be used to output TX_TCLK for MDI Slave jitter measurement.

7.3.2.1 Test Mode 1

Test mode 1 tests the transmitter clock jitter when linked to a partner. In test mode 1, the DP83TG720S-Q1

PHYs are connected over link segment defined in section 97.6 within IEEE 802.3bp. TX_TCLK125 is a divided

clock derived from TX_TCLK, which is one sixth the frequency.

7.3.2.2 Test Mode 2

Test mode 2 tests the transmitter MDI Master mode jitter. In test mode 2, the DP83TG720S-Q1 will transmit a

continuous pattern of three {+1} symbols followed by three {-1} symbols. The transmitted symbols are timed from

the 750-MHz source, which results in a 125-MHz signal.

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

www.ti.com

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