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PDP83TG720SWCSTQ1 bảng dữ liệu(PDF) 62 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY
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PDP83TG720SWCSTQ1 bảng dữ liệu(HTML) 62 Page - Texas Instruments

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7.6.2.6 MII_REG_10 Register (Address = 0x10) [reset = 0x4]
MII_REG_10 is shown in Table 7-29.
Return to the Summary Table.
Table 7-29. MII_REG_10 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-11
RESERVED
R
5b00000
Reserved
10
signal_detect
R/W0S
1b0
Channel ok latch low
1b0 = Channel ok had been reset
1b1 = Channel ok is set
9
descr_lock_bit
R/W0S
1b0
Descrambler lock latch low
1b0 = Descrmabler had been locked
1b1 = Descrambler is locked
8
RESERVED
R
1b0
Reserved
7
mii_int_bit
1b0
Interrupts pin status, cleared on reading 0x12
1b0 = Interrupts pin not set
1b1 = Interrupt pin had been set
6-4
RESERVED
R
3b000
Reserved
3
mii_loopback
R
1b0
MII loopback status
1b0 = No MII loopback
1b1 = MII loopback
2
duplex_mode_env
R
1b1
Duplex mode status
1b0 = Half duplex
1b1 = Full duplex
1
RESERVED
R
1b0
Reserved
0
link_status_bit
R
1b0
Latch low link status
1b0 = link had been down
1b1 = link is up
DP83TG720S-Q1
SNLS604 – SEPTEMBER 2020
www.ti.com
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