PDP83TG720SWCSTQ1 datasheet(37/199 Pages) TI

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Local sleep entry for Slave mode phy :

• Step 1 : Write bit[8] = 'b0 of register[0x0182] register.

• Step 2 : Write bit[7] = 'b1 of register[0x0182] register.

• Step 3 : Make "wake" pin low.

Remote sleep entry for Master mode phy :

• Master mode phy can not be made to enter sleep mode by link-partner

Remote sleep entry for Slave mode phy :

• Step 1 : Write bit[7] = 'b1 of register[0x0182] register.

• Step 2 : Phy will go into sleep mode with loss of energy on line (when master will go quite : no data, no send-

Note

Phy will go into sleep mode only if power supplies are disconnected using INH signal as shown in

figure Required Implementation for Sleep Mode.

7.4.6.4 State Transition #4 - Sleep to Normal

Sleep state can be exited either locally (pin/register-write) or by remote link-partner.

Local sleep exit for Master mode phy by :

• Making "wake" pin high (3.3V).

Local sleep exit for Slave mode phy by :

• Making "wake" pin high (3.3V).

Remote sleep exit for Master mode phy by :

• Link-partner sending TC-10 compliant wake-up energy.

• Link-partner sending 1000BT1 IEEE compliant training signal : "Send-s".

Remote sleep exit for Slave mode phy by :

• Link-partner sending TC-10 compliant wake-up energy.

• Link-partner sending 1000BT1 IEEE compliant training signal : "Send-s".

7.4.7 Media Dependent Interface

7.4.7.1 MDI Master and MDI Slave Configuration

MDI Master and MDI Slave are configured using either hardware bootstraps or through register access.

LED_0 controls the MDI Master and MDI Slave bootstrap configuration. By default, MDI Slave mode is

configured because there is an internal pulldown resistor on LED_0 pin. If MDI Master mode configuration

through hardware bootstrap is preferred, an external pullup resistor is required.

Additionally, bit[14] in the PMA_CTRL2 egister controls the MDI Master and MDI Slave configuration. When this

bit is set, MDI Master mode is enabled.

7.4.7.2 Auto-Polarity Detection and Correction

During the link training process, the DP83TG720S-Q1 as MDI receiver is able to detect polarity reversal and

automatically correct for the error. Both master and slave detects and do the required correction in the receiver

polarity.

7.4.8 MAC Interfaces

7.4.8.1 Reduced Gigabit Media Independent Interface

The DP83TG720S-Q1 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by

RGMII version 2.0. RGMII is designed to reduce the number of pins required to connect MAC and PHY. To

www.ti.com

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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