PDP83TG720SWCSTQ1 datasheet(15/199 Pages) TI

15 / 199 page

(1)

PARAMETER

TEST

CONDITIONS

MIN

NOM

MAX

UNIT

Tfall

Vod Fall Time

100

200

Jitter

Output jitter

300

25 MHz CRYSTAL REQUIREMENTS

Frequency

MHz

Frequency Tolerance and Stability Over temperature and aging

–100

100

ppm

Equivalent Series Resistance

OUTPUT CLOCK TIMING (CLKOUT)

Frequency

MHz

Duty Cycle ( With XI source as 50%)

Rise / Fall Time (10% - 90%)

2.5

Jitter (RMS) (Slave Mode, MAC Iinterface : SGMII)

3.6

Jitter (RMS) (Master Mode, MAC Iinterface : SGMII)

2.4

Jitter (RMS) (Slave Mode, MAC Interface : RGMII)

Jitter (RMS) (Master Mode, MAC Interface : RGMII)

Sleep Entry and Wake-Up

MDI Energy Loss to Sleep Entry; INH Transition LOW

Normal Mode,

WAKE = LOW,

sleep_en = TRUE

Local Wake-Up Pulse Duration

Sleep Mode, WAKE

µs

MDI Energy Detection Wake-Up Pulse Duration

Sleep Mode

0.75

1.25

(1)

Ensured by production test or characterization or design.

(2)

No supply sequencing constraint across power rails

(3)

In case OSC clock is delayed, additional reset is needed post Osc clock stablisation

(4)

Refer register[0x0430] for programmability of RX delay codes

(5)

PHY provides internal delays on TX_CLK to TX_D[3:0] to add additional skew upto 2 ns. Refer to register[0x0430] for programmability

www.ti.com

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

Submit Document Feedback

PDP83TG720SWCSTQ1 bảng dữ liệu(PDF) 15 Page - Texas Instruments

PDP83TG720SWCSTQ1 bảng dữ liệu(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL