PDP83TG720SWCSTQ1 datasheet(41/199 Pages) TI

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7.4.8.2 Serial Gigabit Media Independent Interface

The Serial Gigabit Media Independent Interface (SGMII) provides a means for data transfer between MAC and

PHY with significantly less signal pins (4 pins) compared to RGMII (12 pins). SGMII uses low-voltage differential

signaling (LVDS) to reduce emissions and improve signal quality.

The DP83TG720S-Q1 SGMII is capable of operating in 4-wire mode. In 4-wire operation, two differential pairs

are used to transmit and receive data. Clock and data recovery are performed in the MAC and in the PHY in the

case of the RX and TX directions, respectively.

SGMII Auto-Negotitation can be disabled by setting bit[0] = 0b0 in the SGMII Configuration Register (SGMIICTL,

address 0x608).

The SGMII signals are summarized in Table 7-12.

Table 7-12. SGMII Signals

FUNCTION

PINS

Data Signals

TX_M, TX_P

RX_M, RX_P

Figure 7-17. SGMII Connections

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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