PDP83TG720SWCSTQ1 datasheet(75/199 Pages) TI

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7.6.2.19 LPS_CFG2 Register (Address = 0x18B) [reset = 0x0]

LPS_CFG2 is shown in Table 7-42.

Return to the Summary Table.

Table 7-42. LPS_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-9

RESERVED

7b0000000

Reserved

ed_en

R/W

1b0

1b = Enable energy detection on MDI 0b = Disable energy detection

on MDI

1b0 = Disable energy detection on MDI

1b1 = Enable energy detection on MDI

sleep_en

R/W

1b0

1b = Allow PHY to enter sleep 0b = Do not allow PHY to enter sleep

1b0 = Do not allow PHY to enter sleep

1b1 = Allow PHY to enter sleep

cfg_auto_mode_en_strap

R/WMC,1

1b0

LPS autonomous mode enable 1b = PHY enters normal mode on

power up 0b = PHY enters standby mode on power up

1b0 = PHY enters standby mode on power up

1b1 = PHY enters normal mode on power up

cfg_lps_mon_en_strap

R/W

1b0

1b = Enable normal to standby transition on over temp/under volt 0b

= Disable normal to standby transition on over temp/under volt

1b0 = Disable normal to standby transition on over temp/under volt

1b1 = Enable normal to standby transition on over temp/under volt

cfg_lps_sleep_auto

R/W

1b0

Reserved

cfg_lps_slp_confirm

R/W

1b0

Reserved

cfg_lps_auto_pwrdn

R/W

1b0

Reserved

cfg_lps_sleep_en

R/W

1b0

Reserved

cfg_lps_sm_en

R/W

1b0

Reserved

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DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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