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PDP83TG720SWCSTQ1 bảng dữ liệu(PDF) 63 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 bảng dữ liệu(HTML) 63 Page - Texas Instruments |
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63 / 199 page  7.6.2.7 MII_REG_11 Register (Address = 0x11) [reset = 0xB] MII_REG_11 is shown in Table 7-30. Return to the Summary Table. Table 7-30. MII_REG_11 Register Field Descriptions Bit Field Type Reset Description 15 dis_clk_125 R/W 1b0 Disable MAC clock 1b0 = keep clk_125 to MAC 1b1 = stop clk_125 to MAC on IEEE power save mode 14 power_save_mode_en R/W 1b0 Enable power save mode config from reg 13-12 power_save_mode R/W 2b00 Power mode 2b00 = Normal mode 2b01 = Reserved 2b10 = Active sleep 2b11 = Passive sleep 11 sgmii_soft_reset R/WSC 1b0 Reset SGMII 10 use_phyad0_as_isolate R/W 1b0 Use PHY ADDRESS 5'b0 as isolate 9 channel_debug_mode R/W 1b0 Enable channel debug mode 8 debug_mode R/W 1b0 Enable debug mode 7 RESERVED R 1b0 Reserved 6 cfg_soft_reset_non_clear R/W 1b0 To make 0x1F = 4000 (digital reset) non self clearing 1b11111 = 4000 is self clearing 5-4 cfg_reset_time_sel R/W 2b00 To configure duration of soft reset 00b = 120ns (duration calculated post pll lock) 01b = 32us 10b = 256us 11b = 1024us 2b00 = 120ns 2b01 = 32us 2b10 = 256us 2b11 = 1024us 3 int_polarity R/W 1b1 Interrupts polarity 1b0 = Active high 1b1 = Active low 2 force_interrupt R/W 1b0 Force interrupt pin 1b0 = Do not force interrupt pin 1b1 = Force interrupt pin 1 int_en R/W 1b1 Enable interrupts 1b0 = Disable interrupts 1b1 = Enable interrupts 0 int_oe R/W 1b1 Interrupt/Power down pin configuration 1b0 = PIN is a power down PIN (input) 1b1 = PIN is an interrupt pin (output) www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 63 |
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