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PIC18F2680ISPSQTP bảng dữ liệu(PDF) 289 Page - Microchip Technology |
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PIC18F2680ISPSQTP bảng dữ liệu(HTML) 289 Page - Microchip Technology |
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289 / 482 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39625C-page 287 PIC18F2585/2680/4585/4680 23.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers. REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER Mode 0 R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 RXFUL(1) RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF(2) FILHIT0 Mode 1, 2 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 RXFUL(1) RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6 Mode 0: RXM1: Receive Buffer Mode bit 1 Combines with RXM0 to form RXM<1:0> bits (see bit 5). 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’ 01 = Receive only valid messages with standard identifier; EXIDEN in RXFnSIDL must be ‘0’ 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM0: Receive Buffer Mode bit 0 Combines with RXM1 to form RXM<1:0> bits (see bit 6). Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received bit 4 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: FILHIT4: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits <4:0>. bit 3 Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT3: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits <4:0>. |
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