PIC18F2680ISPSQTP datasheet(60/482 Pages) MICROCHIP

60 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 58

Preliminary

B2CON(6)

2585 2680 4585 4680

0000 0000

uuuu uuuu

B1D7(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1D6(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1D5(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1D4(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1D3(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1D2(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1D1(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1D0(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1DLC(6)

2585 2680 4585 4680

-xxx xxxx

-uuu uuuu

B1EIDL(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1EIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1SIDL(6)

2585 2680 4585 4680

xxxx x-xx

uuuu u-uu

B1SIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B1CON(6)

2585 2680 4585 4680

0000 0000

uuuu uuuu

B0D7(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0D6(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0D5(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0D4(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0D3(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0D2(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0D1(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0D0(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0DLC(6)

2585 2680 4585 4680

-xxx xxxx

-uuu uuuu

B0EIDL(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0EIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0SIDL(6)

2585 2680 4585 4680

xxxx x-xx

uuuu u-uu

B0SIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B0CON(6)

2585 2680 4585 4680

0000 0000

uuuu uuuu

TXBIE(6)

2585 2680 4585 4680

---0 00--

---u uu--

BIE0(6)

2585 2680 4585 4680

0000 0000

uuuu uuuu

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET

Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 4-3 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.

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