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PIC18F2680ISPSQTP bảng dữ liệu(PDF) 42 Page - Microchip Technology |
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PIC18F2680ISPSQTP bảng dữ liệu(HTML) 42 Page - Microchip Technology |
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42 / 482 page ![]() PIC18F2585/2680/4585/4680 DS39625C-page 40 Preliminary © 2007 Microchip Technology Inc. 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to pre- pare for execution. Instruction execution resumes on the first clock cycle following this delay. TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Before Wake-up Clock Source After Wake-up Exit Delay Clock Ready Status Bit (OSCCON) Primary Device Clock (PRI_IDLE mode) LP, XT, HS TCSD(2) OSTS HSPLL EC, RC INTRC(1) — INTOSC(3) IOFS T1OSC or INTRC(1) LP, XT, HS TOST(4) OSTS HSPLL TOST + trc (4) EC, RC TCSD(2) INTRC(1) — INTOSC(2) TIOBST(5) IOFS INTOSC(3) LP, XT, HS TOST(5) OSTS HSPLL TOST + trc (4) EC, RC TCSD(2) INTRC(1) — INTOSC(2) None IOFS None (Sleep mode) LP, XT, HS TOST(4) OSTS HSPLL TOST + trc (4) EC, RC TCSD(2) INTRC(1) — INTOSC(2) TIOBST(5) IOFS Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source. 2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section 3.4 “Idle Modes”). 3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies. 4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is also designated as TPLL. 5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period. |
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