PIC18F2680ISPSQTP datasheet(53/482 Pages) MICROCHIP

53 / 482 page

Preliminary

DS39625C-page 51

PIC18F2585/2680/4585/4680

CCPR1H

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

CCPR1L

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

CCP1CON

2585 2680 4585 4680

--00 0000

--uu uuuu

ECCPR1H

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

ECCPR1L

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

ECCP1CON

2585 2680 4585 4680

0000 0000

uuuu uuuu

BAUDCON

2585 2680 4585 4680

01-0 0-00

--uu uuuu

ECCP1DEL

2585 2680 4585 4680

0000 0000

uuuu uuuu

ECCP1AS

2585 2680 4585 4680

0000 0000

uuuu uuuu

CVRCON

2585 2680 4585 4680

0000 0000

uuuu uuuu

CMCON

2585 2680 4585 4680

0000 0111

uuuu uuuu

TMR3H

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

TMR3L

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

T3CON

2585 2680 4585 4680

0000 0000

uuuu uuuu

SPBRGH

2585 2680 4585 4680

0000 0000

uuuu uuuu

SPBRG

2585 2680 4585 4680

0000 0000

uuuu uuuu

RCREG

2585 2680 4585 4680

0000 0000

uuuu uuuu

TXREG

2585 2680 4585 4680

0000 0000

uuuu uuuu

TXSTA

2585 2680 4585 4680

0000 0010

uuuu uuuu

RCSTA

2585 2680 4585 4680

0000 000x

uuuu uuuu

EEADRH

2585 2680 4585 4680

---- --00

---- --uu

EEADR

2585 2680 4585 4680

0000 0000

uuuu uuuu

EEDATA

2585 2680 4585 4680

0000 0000

uuuu uuuu

EECON2

2585 2680 4585 4680

0000 0000

EECON1

2585 2680 4585 4680

xx-0 x000

uu-0 u000

IPR3

2585 2680 4585 4680

1111 1111

uuuu uuuu

PIR3

2585 2680 4585 4680

0000 0000

uuuu uuuu

PIE3

2585 2680 4585 4680

0000 0000

uuuu uuuu

IPR2

2585 2680 4585 4680

11-1 1111

uu-u uuuu

2585 2680 4585 4680

1--1 111-

u--u uuu-

PIR2

2585 2680 4585 4680

00-0 0000

uu-u uuuu(1)

2585 2680 4585 4680

0--0 000-

u--u uuu-(1)

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET

Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 4-3 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.

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