6402 datasheet(218/250 Pages) INTEL

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Registers

218

Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.6.1.23 WPTRTC1: Write Pointer Timing Control 1

This register determines the DDR I/O FIFO write pointer fine delay timing for DQS17

and DQS8 signals when reading from rank 0 or rank 1.

14.6.1.24 DDQSCVDP and DDQSCADP

This set of 4 registers defines two 64 bit long data patterns used in the DQS Delay

Calibration. They are only used when DCALCSR.BASPAT is low. The 64 bit patterns

cover a data burst that is 32 DRAM clock cycles long. The DDQSCVDP registers define

the “victim” pattern, and the DDQSCADP defines the “aggressor” pattern. The victim

pattern is applied to one bit of each byte of the DDR data bus for 32 clock cycles, and

the aggressor pattern is applied to all other bits. The victim pattern is applied in turn to

each bit of each byte, creating a complete data pattern that is 8*32 data cycles long.

14.6.1.25 DDQSCVDP0: DQS DELAY CAL PATTERN 0

This register defines the last 32 bits of the 64 bit long “victim” data pattern.

14.6.1.26 DDQSCVDP1: DQS DELAY CAL PATTERN 1

This register defines the first 32 bits of the 64 bit long “victim” data pattern.

14.6.1.27 DDQSCADP0: DQS DELAY CAL PATTERN 0

This register defines the last 32 bits of the 64 bit long “aggressor” data pattern.

Device:

NodeID

Function: 4

Offset:

D0h

Bit

Attr

Default

Description

7:4

Reserved

3:0

RWST

DQS01708: Rank 0 DQS17 and DQS8 write pointer fine delay

Device:

NodeID

Function: 4

Offset:

D4h

Bit

Attr

Default

Description

31:0

aaaa0a05h

ENABLE:

Device:

NodeID

Function: 4

Offset:

D8h

Bit

Attr

Default

Description

31:0

5b339c5dh

ENABLE:

Device:

NodeID

Function: 4

Offset:

DCh

Bit

Attr

Default

Description

31:0

aaabffffh

ENABLE:

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