301020013 datasheet(55/109 Pages) AMSOSRAM

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9.1.9

End of range register (Address 0x09)

Table 26: End of range register

Address: 0x09

Default value: 0x7F

Access: Read/Write

Bit

Bit name

Default

Bit description

7:0

End of Range

01111111b

This register is responsible for holding the value to

configure the end of the ADC range (the highest digital

value computed by the ADC). The register holds the 8

MSB's of a 13-bit value (the 5 LSB's are set by hard

wiring to zero). The time in master clock cycles the ADC

requires for a conversion equals the value in this register

multiplied by 32.

Use this register to choose between 10-bit,

11-bit, 12-bit ADC resolution.

The ADC resolution trades versus the ADC conversion

time. Higher resolution thus requires longer line periods,

or the ADC to be run at higher clock frequency.

9.1.10

Test multiplexer register (Address 0x0A)

Table 27: Test multiplexer register

Address: 0x0A

Default value: 0x00(1)

Access: Read/Write

Bit

Bit name

Default

Bit description

7:7

hv_3

This register is responsible for holding the

value to configure the test multiplexer. It

defines the channel (Table 28) that will select

as output for the test multiplexer.

6:6

hv_2

5:5

hv_1

4:4

hv_0

3:3

Test_3

2:2

Test_2

1:1

Test_1

0:0

Test_0

(1) It is recommended to write value 0x0F which helps to stabilize VRef for the chip and reducing significantly line by line offset

noise.

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