301020013 datasheet(50/109 Pages) AMSOSRAM

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9.1.2

Control register 2 (Address 0x02)

Table 18: Control register 2

Address: 0x02

Default value: 0x12

Access: Read/Write

Bit

Bit name

Default value

Bit description

7:6

N/A

00b

Not used

5:5

Analogue Gain

Set to '0' – No analogue gain (x1) in the CDS.

Set to '1' – Analogue gain (x4) in the CDS.

4:4

Enable White Clamping

(Anti-Corona)

Set to '0' – The white clamp is not active.

Set to '1' – The clamping of white values set. White

clamp is used to avoid contrast inversion of heavily

over exposed scenes (corona effect)

3:3

Enable Anti-Blooming(1)

Set to '0' – Additional anti blooming feature OFF.

Set to '1' – Additional anti blooming feature ON.

2:2

White Offset(2)

Set to '0' – Not active, values of the A/D conversion go

to the readout registers.

Set to '1' – When active, a new value is written to the

offset registers.

1:1

Enable Control VRef

Set to '0' – VRef buffer bias is in constant power mode.

Set to '1' – VRef buffer bias in low power mode

(recommended).

0:0

Auto Gen Load Pulse

Set to '0' – The pulse for readout has to be provided

externally.

Set to '1' – The pulse for readout is generated

internally, immediately after completed AD conversion

and once the LVAL of the previous line readout is back

to zero. Multiple readouts of the same data occur if no

new A/D conversion has been started after finalization

of the line readout.

(1) The pixels inherent anti-blooming structures will under normal conditions prevent any kind of blooming. Only under the most

extreme over exposure condition, this additional anti-blooming circuitry may be required.

(2) Feature related to digital subtraction, which is not recommended to be set to ‘1’. Still, if using this feature, the bit 2 in Control

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