T83C5121XXX-ICSIL datasheet(48/115 Pages) ATMEL

48 / 115 page

A/T8xC5121

4164G–SCR–07/06

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 31. Interrupt Vector Addresses

INT1 Interrupt Vector

The INT1 interrupt is multiplexed with the three following inputs:

•INT1/OE: Standard 8051 interrupt input

•

Rxd: Received data on UART

•

CPRES: Insertion or removall of the main card

The setting configurations for each input is detailed below:

INT1/OE Input

This interrupt input is active under the following conditions:

•

It must be enabled thanks to OEEN Bit (ISEL Register)

•

It can be active on a level or falling edge: thanks to IT1 Bit (TCON Register)

•

If level triggering selection is set, the active level 0 or 1 can be selected with OELEV

Bit (ISEL Register)

The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is

cleared when interrupt is processed.

Rxd Input

A second vector interrupt input is the reception of a character. UART Rx input can gen-

erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA

must also be set.

Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on

P3.0/RXD input.

CPRES Input

The third input is the detection of a level change on CPRES input (P1.2). This input can

generate an interrupt if enabled with PRESEN (ISEL.1), EX1 (IE0.2) and EA (IE0.7) Bits.

This detection is done according to the level selected with Bit CPLEV (ISEL.7).

Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are

met. This Bit must be cleared by software.

Interrupt Source

Vector Address

IE0

0003h

TF0

000Bh

IE1 & RxIt & PrIt

0013h

TF1

001Bh

RI & TI

0023h

SCI

0053h

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