T83C5121XXX-ICSIL datasheet(38/115 Pages) ATMEL

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A/T8xC5121

4164G–SCR–07/06

Registers Description

Table 15. SCICR Register

SCICR (S:B6h, SCRS = 1)

Smart Card Interface Control Register

Reset Value = 0000 0000b

RESET

CARDDET

CVcc1

CVcc0

UART

WTEN

CREP

CONV

Bit Number

Bit Mnemonic Description

RESET

Reset

Set this bit to reset the SCIB and its configuration

6CARDDET

Card presence detector sense

Clear this bit to indicate the card presence detector is opened when no card

is inserted (CPRES is high).

Set this bit to indicate the card presence detector is closed when no card is

inserted (CPRES is low).

5 - 4

CVcc[1:0]

Card Voltage Selection:

CVcc[1]

CVcc[0]

CVcc

1.8V

3UART

Card UART selection

Clear this bit to use the Card I/O bit to drive the Card I/O pin.

Set this bit to use the Smart Card UART to drive the Card I/O pin.

Also controls the Wait Time Counter as described in Section “Waiting Time

Counter (WT)”

2WTEN

Wait time counter enable

Clear this bit to stop the counter and enable the load of the Wait Time

counter hold registers.

The hold registers are loaded with SCWT0, SCWT1 and SCWT2 values

when SCWT2 is written.

Set this bit to start the Wait Time counter. The counters stop when it

reaches the timeout value.

If the UART bit is set, the Wait Time counter automatically reloads with the

hold registers whenever a start bit is sent or received.

CREP

Character repetition

Clear this bit to disable parity error detection and indication on the Card I/O

pin in receive mode and to disable character repetition in transmit mode.

Set this bit to enable parity error indication on the Card I/O pin in receive

mode and to set automatic character repetition when a parity error is

indicated in transmit mode. In receive mode, three times error indication is

performed and the parity error flag is set after four times parity error

detection. In transmit mode, up to three times character repetition is

allowed and the parity error flag is set after five times (reset configuration,

can be set at 4 using CREPSET bit in SCSR Register) consecutive parity

error indication.

0CONV

ISO convention

Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the

parity bit is added after b7 bit and a low level on the Card I/O pin represents

a “0”.

Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity

bit is added after b0 bit and a low level on the Card I/O pin represents a “1”.

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