T83C5121XXX-ICSIL datasheet(25/115 Pages) ATMEL

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A/T8xC5121

4164G–SCR–07/06

Table 9. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

Reset Value = X0X0 X000b

432

-WDX2

SIX2

T1X2

T0X2

Bit

Number

Bit

Mnemonic

Description

Reserved

6WDX2

Watchdog clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reserved

4SIX2

Enhanced UART clock (Mode 0 and 2)

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reserved

2T1X2

Timer 1 clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

1T0X2

Timer 0 clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

0X2

CPU clock

Clear to select 12 clock periods per machine cycle (Standard mode) for CPU

and all the peripherals.

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2" bits.

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