T83C5121XXX-ICSIL datasheet(93/115 Pages) ATMEL

93 / 115 page

A/T8xC5121

4164G–SCR–07/06

Reset Value = XXX0 0000b

Table 67. SCON Register

SCON (S:98h)

Serial Control Registe

765

321

FE/SM0

SM1

SM2

REN

TB8

RB8

Bit

Number

Bit

Mnemonic

Description

Framing Error bit

To select this function, set SMOD0 bit in PCON register.

Set by hardware to indicate an invalid stop bit.

Must be cleared by software.

SM0

Serial Port Mode bit 0

To select this function, clear SMOD0 bit in PCON register.

Software writes to bits SM0 and SM1 to select the Serial Port operating mode.

Refer to SM1 bit for the mode selections.

6SM1

Serial Port Mode bit 1

To select this function, set SMOD0 bit in PCON register.

Software writes to bits SM1 and SM0 to select the Serial Port operating mode.

SM0

SM1

Mode Description

Baud Rate

Shift Register

FOSC/12 or variable if SRC bit in BDRCON is set

8-bit UART

Variable

9-bit UART

OSC/32 or FOSC/64

9-bit UART

Variable

5SM2

Serial Port Mode bit 2

Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address

recognition features.

This allows the Serial Port to differentiate between data and command frames and to recognize slave and broadcast

addresses.

4REN

Receiver Enable bit

Clear to disable reception in mode 1, 2 and 3, and to enable transmission in mode 0.

Set to enable reception in all modes.

3TB8

Transmit bit 8

Modes 0 and 1: Not used.

Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.

2RB8

Receiver bit 8

Mode 0: Not used.

Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received.

Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received.

1TI

Transmit Interrupt flag

Set by the transmitter after the last data bit is transmitted.

Must be cleared by software.

0RI

Receive Interrupt flag

Set by the receiver after the stop bit of a frame has been received.

Must be cleared by software.

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