T83C5121XXX-ICSIL datasheet(23/115 Pages) ATMEL

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A/T8xC5121

4164G–SCR–07/06

X2 Feature

The T8xC5121 core needs only 6 clock periods per machine cycle. This feature called

”X2” provides the following advantages:

•

Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

•

Saves power consumption while keeping same CPU power (oscillator power

saving).

•

Saves power consumption by dynamically dividing the operating frequency by 2 in

operating and idle modes.

•

Increases CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

Description

The clock for the whole circuit and peripherals is first divided by two before being used

by the CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio from 40 to 60%.

As shown in Figure 11, X2 bit is validated on the rising edge of the XTAL1

÷2 to avoid

glitches when switching from X2 to standard mode. Figure 12 shows the switching mode

waveforms.

Figure 12. Mode Switching Waveforms

The X2 bit in the CKCON0 register (see Table 9) allows to switch (if CKRL=7) from 12

clock periods per instruction to 6 clock periods and vice versa.

The T0X2, T1X2, UartX2, and WdX2 bits in the CKCON0 register (see Table 9) and

SCX2 bit in the CKCON1 register (see Table 10) allow to switch from standard periph-

eral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock

periods per peripheral clock cycle). These bits are active only in X2 mode.

More information about the X2 mode can be found in the application note "How to Take

Advantage of the X2 Features in TS80C51 Microcontroller?".

XTAL1:2

XTAL1

CPU clock

X2 bit

X2 Mode

STD Mode

FOSC

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