T83C5121XXX-ICSIL datasheet(73/115 Pages) ATMEL

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A/T8xC5121

4164G–SCR–07/06

Timers/Counters

Introduction

The T8xC5121 implements two general-purpose, 16-bit Timer 0s/Counters. Although

they are identified as Timer 0, Timer 1, you can independently configure each to operate

in a variety of modes as a Timer 0 or as an event Counter. When operating as a Timer 0,

a Timer 0/Counter runs for a programmed length of time, then issues an interrupt

request. When operating as a Counter, a Timer 0/Counter counts negative transitions

on an external pin. After a preset number of counts, the Counter issues an interrupt

request.

The Timer 0 registers and associated control registers are implemented as addressable

Special Function Registers (SFRs). Two of the SFRs provide programmable control of

the Timer 0s as follows:

•

Timer 0/Counter mode control register (TMOD) and Timer 0/Counter control register

(TCON) control respectively Timer 0 and Timer 1.

The various operating modes of each Timer 0/Counter are described below.

Timer 0/Counter

Operations

For example, a basic operation is Timer 0 registers THx and TLx (x = 0, 1) connected in

cascade to form a 16-bit Timer 0. Setting the run control bit (TRx) in the TCON register

(see Figure 55) turns the Timer 0 on by allowing the selected input to increment TLx.

When TLx overflows it increments THx and when THx overflows it sets the Timer 0 over-

flow flag (TFx) in the TCON register. Setting the TRx does not clear the THx and TLx

Timer 0 registers. Timer 0 registers can be accessed to obtain the current count or to

enter preset values. They can be read at any time but the TRx bit must be cleared to

preset their values, otherwise the behavior of the Timer 0/Counter is unpredictable.

The C/Tx# control bit selects Timer 0 operation or Counter operation by selecting the

divided-down system clock or the external pin Tx as the source for the counted signal.

The TRx bit must be cleared when changing the operating mode, otherwise the behavior

of the Timer 0/Counter is unpredictable.

For Timer 0 operation (C/Tx# = 0), the Timer 0 register counts the divided-down system

clock. The Timer 0 register incremented once every peripheral cycle.

Exceptions are the Timer 0 2 Baud Rate and Clock-Out modes in which the Timer 0 reg-

ister is incremented by the system clock divided by two.

For Counter operation (C/Tx# = 1), the Timer 0 register counts the negative transitions

on the Tx external input pin. The external input is sampled during every S5P2 state. The

Programmer’s Guide describes the notation for the states in a peripheral cycle. When

the sample is high in one cycle and low in the next one, the Counter is incremented. The

new count value appears in the register during the next S3P1 state after the transition

has been detected. Since it takes 12 states (24 oscillator periods) to recognize a nega-

tive transition, the maximum count rate is 1/24 of the oscillator frequency. There are no

restrictions on the duty cycle of the external input signal, but to ensure that a given level

is sampled at least once before it changes, it should be held for at least one full periph-

eral cycle.

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