T83C5121XXX-ICSIL datasheet(87/115 Pages) ATMEL

87 / 115 page

A/T8xC5121

4164G–SCR–07/06

Figure 37. Internal Baud Rate Generator Block Diagram

Synchronous Mode (Mode 0)

Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0

capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of

eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data.

The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur

at a fixed Baud Rate. Figure 38 shows the serial port block diagram in Mode 0.

Figure 38. Serial I/O Port Block Diagram (Mode 0)

Transmission (Mode 0)

To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.

As shown in Figure 39, writing the byte to transmit to SBUF register starts the transmis-

sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle

composed of a high level then low level signal on TXD. During the eighth clock cycle the

MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to

indicate the end of the transmission.

Figure 39. Transmission Waveforms (Mode 0)

Overflow

SPD

BDRCON.1

BRG

(8 bits)

BRL

(8 bits)

PER

CLOCK

÷ 6

IBRG

CLOCK

BRR

BDRCON.4

SMOD1

PCON.7

÷ 2

To Serial Port

BRG

CLOCK

TXD

RXD

SBUF Tx SR

SBUF Rx SR

SM1

SCON.6

SM0

SCON.7

Mode Decoder

M3 M2 M1 M0

Mode

Controller

SCON.0

SCON.1

PER

CLOCK

Baud Rate

Controller

Write to SBUF

TXD

RXD

T83C5121XXX-ICSIL bảng dữ liệu(PDF) 87 Page - ATMEL Corporation

T83C5121XXX-ICSIL bảng dữ liệu(HTML) 87 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL