T83C5121XXX-ICSIL datasheet(27/115 Pages) ATMEL

27 / 115 page

A/T8xC5121

4164G–SCR–07/06

DC/DC Clock

The DC/DC block needs a clock with a 50% duty cycle. The frequency must also respect

a value between 3.68 MHz and 4 MHz. The first requirement imposes a divider in the

clock path and the second constraint is solved with the use of a prescaler.

Figure 13. Functional Block Diagram

Clock Control Register

This register is used to reload the clock prescaler of the DC/DC converter clock.

Table 11. DCCKPS Register

DCCKPS - DC/DC converter Reload Register (BFh)

Reset Value = XXXX XX11b

Clock Prescaler

Before supplying the DC/DC block, the oscillator clock is divided by a factor 2 to 5 to

adapt the clock needed by the DC/DC converter. This factor is controlled with the

DCCKPS register.

The prescaler factor must be chosen to match the requirement range which is 4MHz.

Table 12. Examples of Factors

CLK_DC/DC

FOSC

2 to 5

(2 to 5)

DCCKPS

Address BFh

DCCKPS

Bit

Number

Bit

Mnemonic

Description

7:2

Reserved

Do not use write those bits

1:0

DCCKPS

Clock Reload Register

Prescaler value

00b: Division factor equals 2

01b: division factor equals 3

10b: division factor equals 4

11b: division factor equals 5 (reset value which minimize the consumption)

XTAL (MHz)

DCCKPS Value

Prescaler

Factor

DC/DC Converter CLK (MHz)

800h

01h

14.756

02h

3.689

02h

03h

T83C5121XXX-ICSIL bảng dữ liệu(PDF) 27 Page - ATMEL Corporation

T83C5121XXX-ICSIL bảng dữ liệu(HTML) 27 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL