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T83C5121XXX-ICSIL bảng dữ liệu(PDF) 97 Page - ATMEL Corporation

tên linh kiện T83C5121XXX-ICSIL
Giải thích chi tiết về linh kiện  8-bit Microcontroller with Multiprotocol Smart Card Interface
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97
A/T8xC5121
4132C–SCR–07/06
Table 71. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
WDT during Power-down
and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as it normally should whenever the
T8xC5121 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is better to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
T8xC5121 while in Idle mode, the user should always set up a timer that will periodically
exit Idle, service the WDT, and re-enter Idle mode.
76
54
32
1
0
-
-
-
-
-
S2
S1
S0
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6-
5-
4-
3-
2S2
WDT Time-out select bit 2
1S1
WDT Time-out select bit 1
0S0
WDT Time-out select bit 0
S2
S1
S0
Selected Time-out
00
0
(214 - 1) machine cycles, 16. 3 ms @ F
OSCA =12 MHz
00
1
(215 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
01
0
(2
16 - 1) machine cycles, 65. 5 ms @ F
OSCA=12 MHz
01
1
(217 - 1) machine cycles, 131 ms @ F
OSCA=12 MHz
10
0
(218 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
10
1
(2
19 - 1) machine cycles, 542 ms @ F
OSCA=12 MHz
11
0
(220 - 1) machine cycles, 1.05 ms @ F
OSCA=12 MHz
11
1
(221 - 1) machine cycles, 2.09 ms @ FOSCA=12 MHz



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