PI7C8150ANDE datasheet(91/111 Pages) PERICOM

91 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 91 of 111

APRIL 2006 – Revision 1.1

Bit

Function

Type

Description

Target Abort

During Posted

Write

R/W

Controls PI7C8150A’s ability to assert P_SERR_L when it receives a

target abort when attempting to deliver posted write data.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

Master Abort On

Posted Write

R/W

Controls PI7C8150A’s ability to assert P_SERR_L when it receives a

master abort when attempting to deliver posted write data.

0: P_SERR# is asserted if this event occurs and the SERR# enable bit

in the command register is set

1: P_SERR# is not asserted if this event occurs

Reset to 0

Delayed Write

Non-Delivery

R/W

Controls PI7C8150A’s ability to assert P_SERR# when it is unable to

transfer delayed write data after 2

24 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

Delayed Read –

No Data From

Target

R/W

Controls PI7C8150A’s ability to assert P_SERR_L when it is unable

to transfer any read data from the target after 2

24 attempts.

0: P_SERR_L is asserted if this event occurs and the SERR_L enable

bit in the command register is set

1: P_SERR_L is not asserted if this event occurs

Reset to 0

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

14.1.39

GPIO DATA AND CONTROL REGISTER – OFFSET 64h

Bit

Function

Type

Description

11:8

GPIO Output

Write-1-to-Clear

R/WC

Writing 1 to any of these bits drives the corresponding bit LOW on

the GPIO[3:0] bus if it is programmed as bidirectional. Data is

driven on the PCI clock cycle following completion of the

configuration write to this register. Bit positions corresponding to

GPIO pins that are programmed as input only are not driven. Writing

0 has no effect and will show last the last value written when read.

Reset to 0.

15:12

GPIO Output

Write-1-to-Set

R/WS

Writing 1 to any of these bits drives the corresponding bit HIGH on

the GPIO[3:0] bus if it is programmed as bidirectional. Data is

driven on the PCI clock cycle following completion of the

configuration write to this register. Bit positions corresponding to

GPIO pins that are programmed as input only are not driven. Writing

0 has no effect and will show last the last value written when read.

Reset to 0.

06-0057

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