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PI7C8150ANDE bảng dữ liệu(PDF) 83 Page - Pericom Semiconductor Corporation |
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PI7C8150ANDE bảng dữ liệu(HTML) 83 Page - Pericom Semiconductor Corporation |
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83 / 111 page ![]() PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 83 of 111 APRIL 2006 – Revision 1.1 Bit Function Type Description 29 Received Master Abort R/WC Set to 1 (by a master) when transactions on its secondary interface are terminated with Master Abort Reset to 0 30 Received System Error R/WC Set to 1 when S_SERR_L is asserted Reset to 0 31 Detected Parity Error R/WC Set to 1 when address or data parity error is detected on the secondary interface Reset to 0 14.1.17 MEMORY BASE REGISTER – OFFSET 20h Bit Function Type Description 3:0 R/O Lower four bits of register are read only and return 0. Reset to 0 15:4 Memory Base Address [15:4] R/W Defines the bottom address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be 0. Reset to 0 14.1.18 MEMORY LIMIT REGISTER – OFFSET 20h Bit Function Type Description 19:16 R/O Lower four bits of register are read only and return 0. Reset to 0 31:20 Memory Limit Address [31:20] R/W Defines the top address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh. 14.1.19 PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h Bit Function Type Description 3:0 64-bit addressing R/O Indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing Reset to 1 15:4 Prefetchable Memory Base Address [31:20] R/W Defines the bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be 0. 06-0057 |
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