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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PI7C8150ANDE bảng dữ liệu(PDF) 60 Page - Pericom Semiconductor Corporation |
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PI7C8150ANDE bảng dữ liệu(HTML) 60 Page - Pericom Semiconductor Corporation |
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60 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 60 of 111 APRIL 2006 – Revision 1.1 The PI7C8150A must be a master on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. The S_PERR_L signal is detected asserted or a parity error is detected on the secondary bus. Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit Secondary Detected Parity Detected Bit Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits 0 Read Downstream Primary x / x 1 Read Downstream Secondary x / 1 0 Read Upstream Primary x / x 0 Read Upstream Secondary x / x 0 Posted Write Downstream Primary x / x 1 Posted Write Downstream Secondary x / 1 0 Posted Write Upstream Primary x / x 0 Posted Write Upstream Secondary x / x 0 Delayed Write Downstream Primary x / x 1 Delayed Write Downstream Secondary x / 1 0 Delayed Write Upstream Primary x / x 0 Delayed Write Upstream Secondary x / x X= don’t care Table 6-5 shows assertion of P_PERR_L. This signal is set under the following conditions: PI7C8150A is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be set in the command register of primary interface. PI7C8150A detects a data parity error on the primary bus or detects S_PERR_L asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus. Table 6-5. Assertion of P_PERR_L P_PERR_L Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits 1 (de-asserted) Read Downstream Primary x / x 1 Read Downstream Secondary x / x 0 (asserted) Read Upstream Primary 1 / x 1 Read Upstream Secondary x / x 0 Posted Write Downstream Primary 1 / x 1 Posted Write Downstream Secondary x / x 1 Posted Write Upstream Primary x / x 1 Posted Write Upstream Secondary x / x 0 Delayed Write Downstream Primary 1 / x 0 2 Delayed Write Downstream Secondary 1 / 1 1 Delayed Write Upstream Primary x / x 1 Delayed Write Upstream Secondary x / x 06-0057 |
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