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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PI7C8150ANDE bảng dữ liệu(PDF) 59 Page - Pericom Semiconductor Corporation |
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PI7C8150ANDE bảng dữ liệu(HTML) 59 Page - Pericom Semiconductor Corporation |
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59 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 59 of 111 APRIL 2006 – Revision 1.1 X = don’t care Table 6-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C8150A detects a parity error on the secondary interface. Table 6-2. Setting Secondary Interface Detected Parity Error Bit Secondary Detected Parity Error Bit Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits 0 Read Downstream Primary x / x 1 Read Downstream Secondary x / x 0 Read Upstream Primary x / x 0 Read Upstream Secondary x / x 0 Posted Write Downstream Primary x / x 0 Posted Write Downstream Secondary x / x 0 Posted Write Upstream Primary x / x 1 Posted Write Upstream Secondary x / x 0 Delayed Write Downstream Primary x / x 0 Delayed Write Downstream Secondary x / x 0 Delayed Write Upstream Primary x / x 1 Delayed Write Upstream Secondary x / x X = don’t care Table 6-3 shows setting data parity detected bit in the primary interface’s status register. This bit is set under the following conditions: PI7C8150A must be a master on the primary bus. The parity error response bit in the command register, corresponding to the primary interface, must be set. The P_PERR_L signal is detected asserted or a parity error is detected on the primary bus. Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit Primary Data Parity Bit Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits 0 Read Downstream Primary x / x 0 Read Downstream Secondary x / x 1 Read Upstream Primary 1 / x 0 Read Upstream Secondary x / x 0 Posted Write Downstream Primary x / x 0 Posted Write Downstream Secondary x / x 1 Posted Write Upstream Primary 1 / x 0 Posted Write Upstream Secondary x / x 0 Delayed Write Downstream Primary x / x 0 Delayed Write Downstream Secondary x / x 1 Delayed Write Upstream Primary 1 / x 0 Delayed Write Upstream Secondary x / x X = don’t care Table 6-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: 06-0057 |
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