TMPR4925 datasheet(307/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-45

10.4.19 P2G Status Register (P2GSTATUS)

0xD094

Reserved

: Type

: Initial value

321

Reserved

TOBFE TIBFE PMSC PERR

GBE

R/W1C R/W1C R/W1C : Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:5



Reserved



TOBFE

Target Out-Bound

FIFO Empty

Target Out-Bound FIFO Empty (Initial value: 1, R)

1: Indicates that the Target Out-Bound FIFO is empty.

0: Indicates that the Target Out-Bound FIFO is not empty.

This is a diagnostic function.

3TIBFE

Target In-Bound

FIFO Empty

Target In-Bound FIFO Empty (Initial value: 1, R)

1: Indicates that the Target In-Bound FIFO is empty.

0: Indicates that the Target In-Bound FIFO is not empty.

This is a diagnostic function.

PMSC

PM State Change

Detected

Power Management State Change (Initial value: 0, R/W1C)

“1” is set to this bit when the PowerState field of the Power Management Register

(PMCSR) is rewritten.

This bit is cleared to “0” when a “1” is written to it. This bit is only valid when the PCI

Controller is in the Satellite mode.

PERR

PERR* Detected

PERR* Occurred (Initial value: 0, R/W1C)

Indicates that a Parity error occurred during Target access.

1: Indicates that a Parity error occurred.

0: Indicates that no Parity error has occurred..

0TGBE

Target G-Bus

Error Detect

Target G-Bus Error Detect (Initial value: 0, R/W1C)

Indicates that a G-Bus Error occurred when the G-Bus was Target of the PCI cycle.

This error is indicated when a timeout occurs on the G-Bus. This bit is only set during

PCI Target cycle Bus Errors.

1: Indicates that a G-Bus Error was detected.

0: Indicates that no G-Bus Error was detected.

Figure 10.4.19 P2G Status Register

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