TMPR4925 datasheet(305/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-43

10.4.17 PCI Status Interrupt Mask Register (PCIMASK)

0xD08C

Reserved

: Type

: Initial value

DPEIE SSEIE RMAIE RTAIE STAIE

Reserved

MDPEIE

Reserved

R/W

: Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:16



Reserved



DPEIE

Detected Parity

Error Interrupt

Enable

Detected Parity Error Interrupt Enable (Initial value: 0, R/W)

Generates an interrupt when a parity error is detected.

Usually, this interrupt is masked and a Master Data Parity error signals the error to the

system.

1: Generates an interrupt.

0: Does not generate an interrupt.

SSEIE

Signaled System

Error Interrupt

Enable

Signaled System Error Interrupt Enable (Initial value: 0, R/W)

Generates an interrupt when a system error is signaled.

1: Generates an interrupt.

0: Does not generate an interrupt.

RMAIE

Received Master

Abort Interrupt

Enable

Received Master Abort Interrupt Enable (Initial value: 0, R/W)

Generates an interrupt when a Master Abort is received.

1: Generates an interrupt.

0: Does not generate an interrupt.

RTAIE

Received Target

Abort Interrupt

Enable

Received Target Abort Interrupt Enable (Initial value: 0, R/W)

Generates an interrupt when a Target Abort is received.

1: Generates an interrupt.

0: Does not generate an interrupt.

STAIE

Signaled Target

Abort Interrupt

Enable

Signaled Target Abort Interrupt Enable (Initial value: 0, R/W)

Generates an interrupt when a Target Abort is signaled.

1: Generates an interrupt.

0: Does not generate an interrupt.

10:9



Reserved



8MDPEIE

Master Data

Parity Detected

Interrupt Enable

Master Data Parity Detected Interrupt Enable (Initial value: 0, R/W)

Generates an interrupt when data parity is detected.

1: Generates an interrupt.

0: Does not generate an interrupt.

7:0



Reserved



Figure 10.4.17 PCI Status Interrupt Mask Register

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