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TMPR4925 bảng dữ liệu(PDF) 201 Page - Toshiba Semiconductor

tên linh kiện TMPR4925
Giải thích chi tiết về linh kiện  64-Bit TX System RISC TX49 Family
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMPR4925 bảng dữ liệu(HTML) 201 Page - Toshiba Semiconductor

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Chapter 8 DMA Controller
8-31
8.4.5
DMA Destination Address Register (DMDARn)
0xB008 (ch. 0)
0xB028 (ch. 1)
0xB048 (ch. 2)
0xB068 (ch. 3)
31
16
DADDR[31:16]
R/W
: Type
-
: Initial value
15
0
DADDR[15:0]
R/W
: Type
-
: Initial value
Bits
Mnemonic
Field Name
Description
31:0
DADDR
Destination
Address
Destination Address (Initial value: undefined, R/W)
This register sets the physical address of the transfer destination during Dual
Address transfer. This register is ignored during Single Address transfer.
Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more
information.
During Burst transfer, the value changes only by the size of data transferred during
each single bus operation. During Single transfer, the value only changes by the
value specified by the DMA Destination Address Increment Register (DMDAIRn).
Figure 8.4.5 DMA Destination Address Register



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