TMPR4925 datasheet(199/590 Pages) TOSHIBA

199 / 590 page

Chapter 8 DMA Controller

8-29

Bits

Mnemonic

Field Name

Description

XFACT

Transfer Active

Transfer Active (Initial value: 0, R)

This value is a copy of the Transfer Active bit (XFACT) of the DMA Channel Control

ABCHC

Error Complete

Error Completion (Initial value: 0, R)

This bit indicates whether an error occurred during DMA transfer. This bit indicates

the logical sum of the four error bits (CFERR, CHERR, DESERR, SORERR) in

DMCSRn[3:0].

1: DMA transfer ends due to an error.

0: No error occurred since this bit was last cleared.

NCHNC

Chain Complete

Normal Chain Completion (Initial value: 0, R/W1C)

When performing chain DMA transfer, This bit indicates whether all DMA data

transfers in the DMA Descriptor chain are complete.

1: All DMA data transfers in the DMA Descriptor chain ended normally. Or, DMA

transfer that did not use a DMA Descriptor chain ended normally.

0: DMA transfer has not ended normally since this bit was last cleared.

5NTRNFC

Transfer

Complete

Normal Transfer Completion (Initial value: 0, R/W1C)

This bit indicates whether DMA transfer ended according to the current DMA Channel

1: DMA transfer ended normally.

0: DMA transfer has not ended since this bit was last cleared.

4EXTDN

External DONE

Asserted

External Done Asserted (Initial value: 0, R/W1C)

This bit indicates whether an external I/O device asserted the DMADONE* signal.

When the DMADONE* signal is set to bidirectional, this bit is also set when the

TX4925 asserts the DMADONE* signal.

1: DMADONE* signal was asserted.

0: DMADONE* signal was not asserted.

3CFERR

Configuration

Error

Configuration Error (Initial value: 0, R/W1C)

Indicates whether an illegal register setting was made.

1: There was a configuration error.

0: There was no configuration error.

CHERR

Chain Bus Error

Chain Bus Error (Initial value: 0, R/W1C)

This bit indicates whether a bus error occurred while reading a DMA Command

Descriptor.

1: Bus error occurred.

0: No bus error occurred.

DESERR

Destination Error

Destination Bus Error (Initial value: 0, R/W1C)

This bit indicates whether a bus error occurred during a destination bus Write

operation (a Write to a set DMDARn address).

1: Bus error occurred.

0: No bus error occurred.

SORERR

Source Bus Error

Source Bus Error (Initial value: 0, R/W1C)

This bit indicates whether a bus error occurred during either a source bus Read or

Write operation (A Read or Write to a set DMSARn address).

1: Bus error occurred.

0: No bus error occurred.

Figure 8.4.3 DMA Channel Status Register (2/2)

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