TMPR4925 datasheet(200/590 Pages) TOSHIBA

tên linh kiện	TMPR4925

Giải thích chi tiết về linh kiện	64-Bit TX System RISC TX49 Family

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Chapter 8 DMA Controller

8-30

8.4.4

DMA Source Address Register (DMSARn)

0xB004 (ch. 0)

0xB024 (ch. 1)

0xB044 (ch. 2)

0xB064 (ch. 3)

SADDR[31:16]

R/W

: Type

: Initial value

SADDR[15:0]

R/W

: Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:0

SADDR

Source Address

Source Address (Initial value: undefined, R/W)

This field sets the physical address of the transfer source during Dual Address

transfer. This field sets the physical address of memory access during Single

Address transfer. This field is used for either Memory-to-I/O or I/O-to-Memory

transfers.

Refer to “8.3.7.1 Channel Register Settings During Single Address Transfer” and

“8.3.8.1 Channel Register Settings During Dual Address Transfer” for more

information.

During Burst transfer, the value changes once for each bus operation only by the size

that was transferred. During Single transfer, the value only changes by the value

specified by the DMA Source Address Increment Register (DMSAIRn).

Figure 8.4.4 DMA Source Address Register

TMPR4925 bảng dữ liệu(PDF) 200 Page - Toshiba Semiconductor