TMPR4925 datasheet(188/590 Pages) TOSHIBA

188 / 590 page

Chapter 8 DMA Controller

8-18

If an error is detected during DMA transfer, the error cause is recorded in the lower four bits of the

DMA Channel Status register and transfer is interrupted. An interrupt is signalled if the Error

Interrupt Enable bit (INTENE) of the DMA Channel Control Register is set.

8.3.11

Dynamic Chain Operation

It is possible to add DMA Command Descriptor chains to the DMA Command Descriptor chain

while Chain DMA transfer is in progress. This is performed according to the following procedure. This

procedure is available only when the value of the last descriptor DMSAIRn/DMDAIRn in the last

command descriptor chain is one or more than one byte.

(1) Construct the DMA Command Descriptor chain

Construct the DMA Command Descriptor chain to be added to memory.

(2) Add a DMA Command Descriptor chain

Substitute the address of the Command Descriptor at the beginning of the Descriptor Chain to be

added into the Chain Address field of the Descriptor at the end of the DMA Command Descriptor

chain that is currently performing DMA transfer.

(3) Check the Chain Enable bit

Read the value of the Chain Enable bit (CHNEN) of the DMA Channel Control Register

(DMCCRn). If that value is “0”, then write the Chain Address field value of the DMA Command

Descriptor that is indicated by the address stored in the DMA Chain Address Register

(DMCHARn).

8.3.12

Interrupts

An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition,

there are completion interrupts for when transfer ends normally and error interrupts for when transfer

ends abnormally for each channel. When an interrupt occurs, then the bit that corresponds to either the

Normal Interrupt Status field (DIS[3:0]) or the Error Interrupt Status field (EIS[3:0]) of the DMA

Master Control Register (DMMCR) is set.

Figure 8.3.6 shows the relationship between the Status bit and Interrupt Enable bit for each interrupt

cause. Refer to the explanation for each Status bit for more information regarding each information

cause.

Figure 8.3.6 DMA Controller Interrupt Signal

DMMCR.DIS[n]

DMCSRn.CFERR

DMCSRn.CHERR

DMCSRn.DESERR

DMCSRn.SORERR

DMCSRn.STLXFER

DMMCR.EIS[n]

DMCCRn.INTENE

DMCSRn.NCHNC

DMCCRn.INTENC

DMCSRn.NTRNFC

DMCCRn.INTENT

Interrupt Controller

(Interrupt No. 10 – 13)

DMCSRn.ABCHC

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