TMPR4925 datasheet(186/590 Pages) TOSHIBA

186 / 590 page

Chapter 8 DMA Controller

8-16

8.3.10

Chain DMA Transfer

Table 8.3.4 shows the data structure in memory that the DMA Command Descriptor has. When the

Simple Chain bit (SMPCHN) of the DMA Channel Control Register (DMCCRn) is set, only the initial

four words are used. DMSAIRn, DMDAIR, DMCCRn, and DMCSRn use the settings from when

DMA started. In addition, all eight words are used when the Simple Chain bit (SMPCHN) is cleared.

Saving the start memory address of another DMA Command Descriptor in the Offset 0 Chain

Address field makes it possible to construct a chain list of DMA Command Descriptors (Figure 8.3.5).

Set “0” in the Chain Address field of the DMA Command Descriptor at the end of the chain list.

When DMA transfer that is specified by one DMA Command Descriptor ends, the DMA Controller

automatically reads the next DMA Command Descriptor indicated by the Chain Address Register

(Chain transfer), then continues DMA transfer. Continuous DMA transfer that uses multiple Descriptors

connected into such a chain-like structure is called Chain DMA transfer.

Since the DMA Channel Status Register is also overwritten during Chain transfer when the DMA

Simple Chain bit (SMPCHN) is cleared, be sure not to unnecessarily clear necessary bits.

Placing DMA Command Descriptors at addresses that do not span across 32 word boundaries in

memory is efficient since they are read by one G-Bus Burst Read operation.

Table 8.3.4 DMA Command Descriptors

Offset Address

Field Name

Transfer Destination Register

0x00

Chain Address

DMA Chain Address Register (DMCHARn)

0x04

Source Address

DMA Source Address Register (DMSARn)

0x08

Destination Address

DMA Destination Address Register (DMDARn)

0x0c

Count

DMA Count Register (DMCNTRn)

0x10

Source Address Increment

DMA Source Address Increment Register (DMSAIRn)

0x14

Destination Address Increment

DMA Destination Address Increment Register (DMDAIRn)

0x18

Channel Control

DMA Channel Control Register (DMCCRn)

0x1c

Channel Status

DMA Channel Status Register (DMCSRn)

Figure 8.3.5 DMA Command Descriptor Chain

“A”

+04

+08

+0c

+10

+14

+18

+1c

“B”

+04

+08

+0c

+10

+14

+18

+1c

“C”

+04

+08

+0c

+10

+14

+18

+1c

“D”

+04

+08

+0c

+10

+14

+18

+1c

“E”

+04

+08

+0c

+10

+14

+18

+1c

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