TMPR4925 datasheet(358/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-96

Bits

Mnemonic

Field Name

Description

6:5



Reserved



PCIPERR

PCI Parity Error

PCI Parity Error (Initial value: 0, R/W1C)

1: Indicates that there was a parity error on a PCI transaction performed on behalf of

the PDMAC.

0: Indicates that no parity error has been detected on PDMAC PCI transfer since this

bit was cleared.

PCISERR

PCI System Error

PCI System Error (Initial value: 0, R/W1C)

1: Indicates that a PCI bus module asserted SERR* during a PCI operation initiated

by the PDMAC.

0: Indicates that SERR* has not been asserted during a PDMAC-initiated PCI cycle

since this bit was last cleared.

PCIERR

PCI Fatal Error

PCI Fatal Error (Initial value: 0, R/W1C)

1: Indicates that an error was signaled on the PCI Bus during a PCI operation initiated

by the PDMAC.

0: Indicates that no error has been signaled on the PCI Bus since this bit was

previously cleared.

1CHNERR

G-Bus Chain

Error

G-Bus Chain Bus Error (Initial value: 0, R/W1C)

1: Indicates that a G-Bus error occurred during the Chain process. DMA transfer

stops.

0: Indicates that no G-Bus error has occurred during the Chain process since this bit

was cleared.

DATAERR

G-Bus Data Error

G-Bus Data Bus Error (Initial value: 0, R/W1C)

1: Indicates that a G-Bus error occurred during the data transfer process. DMA

transfer stops.

0: Indicates that no G-Bus error has occurred during the data transfer process since

this bit was cleared.

Figure 10.4.66 PDMAC Status Register (2/2)

Figure 10.4.67 PDMAC Interrupt Signaling

DONEINT

PCISE

PCIERR

CHNERR

DATAERR

PCIPE

ERRINT

ERRIE

NCCMP

NCCMPIE

NTCMP

NTCMPIE

Interrupt Controller

(Interrupt No. 15)

ACCMP

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