TMPR4925 datasheet(355/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-93

10.4.65 PDMAC Configuration Register (PDMCFG)

0xD210

Reserved

RSTFIFO

BSWAP

GBRSTI

Reserved

R/W

: Type

: Initial value

Reserved

REQDLY

ERRIE NCCMPIE NTCMPIE CHNEN XFRACT

Reserved

XFRMODE

XFRDIRC

CHRST

R/W

R/W : Type

000

: Initial value

Bits

Mnemonic

Field Name

Description

31:22



Reserved



RSTFIFO

Reset FIFO

Reset FIFO (Initial value: 0, R/W)

Initializes the Read pointer and Write pointer to the FIFO in the PDMAC, and sets the

FIFO hold count to “0”. Please use the software to clear this bit when it is set.

1: Performs FIFO reset.

0: Does not perform FIFO reset.

BSWAP

Byte Swap Within

DWORD

Swap Bytes in DWORD (Initial value: 0, R/W)

Specifies whether to perform 32-bit data byte swapping.

Please leave this bit at “0” for normal usage.

Setting this bit when in the Big Endian mode executes data transfer so the byte order

of the 32-bit data on the PCI Bus (which is Little Endian) does not change.

1: Transfer without swapping the byte order of each 32-bit DWORD data.

0: Swap the byte order of each 32-bit DWORD data, then transfer.

GBRSTI

G-Bus Burst

Inhibit

G-Bus Burst Inhibit (Initial value: 0, R/W)

1: Do not use burst operations on G-Bus even if the burst mode field specifies burst.

This allows devices that can’t burst to transfer data using bursts on the PCI bus.

This bit applies only to G-Bus data transfers; it has no affect on chain operations.

0: The MDA will use burst operations for G-Bus data transfers when programmed to

do so and if alignment, count, etc. permit.

18:14



Reserved



13:11

REQDLY

Request Delay

Time

Request Delay (Initial value: 0x0, R/W)

G-Bus transactions for DMA transfer must be performed separated at least by the

interval this field specifies.

000:

Continuously try to perform G-Bus transfer.

001:

16 G-Bus clocks

010:

32 G-Bus clocks

011:

64 G-Bus clocks

100:

128 G-Bus clocks

101:

256 G-Bus clocks

110:

512 G-Bus clocks

111:

1024 G-Bus clocks

ERRIE

Error Detect

Interrupt Enable

Interrupt Enable on Error (Initial value: 0, R/W)

1: PDMAC generates an error during error detection.

0: PDMAC does not generate an error during error detection.

NCCMPIE

Normal Chain

Complete

Interrupt Enable

Interrupt Enable on Chain Done (Initial value: 0, R/W)

1: PDMAC generates an interrupt when the current chain is complete.

0: PDMAC does not generate an interrupt when the current chain is complete.

NTCMPIE

Normal Data

Transfer

Complete

Interrupt Enable

Interrupt Enable on Transfer Done (Initial value: 0, R/W)

1: PDMAC generates an interrupt when the current data transfer is complete.

0: PDMAC does not generate an interrupt when the current data transfer is complete.

Figure 10.4.65 PDMAC Configuration Register (1/2)

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