TMPR4925 datasheet(357/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-95

10.4.66 PDMAC Status Register (PDMSTATUS)

0xD214

Reserved

FIFOCNT

FIFOWP

FIFORP

: Type

00000

0x0

: Initial value

Reserved

PCIACT ERRINT DONEINT CHNEN XFRACT ACCMP NCCMP NTCMP

Reserved

PCIPERR PCISERR

PCIERR CHNERR DATAERR

R/W1C R/W1C

R/W1C R/W1C R/W1C R/W1C R/W1C : Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:29



Reserved



28:24

FIFOCNT

FIFO Hold Count

FIFO Valid Entry Count (Initial value: 00000, R)

This field indicates the number of DWORDs written to the FIFO but not yet read. This

is a diagnostic function.

23:20

FIFOWP

FIFO Write

Pointer

FIFO Write Pointer (Initial value: 0x0, R)

This field indicates the next Write position in the FIFO. This is a diagnostic function.

19:16

FIFORP

FIFO Read

Pointer

FIFO Read Pointer (Initial value: 0x0, R)

This field indicates the next Read position in the FIFO. This is a dianostic function.



Reserved



PCIACT

PCI Active

PCI Active (Initial value: 0, R)

1: The PDMAC is requesting to transfer data to or from the PCI bus of it is currently

transferring data.

0: There is no active request or transfer from the PDMAC for the PCI bus.

ERRINT

Error Interrupt

Status

Error Interrupt Status (Initial value: 0, R)

Indicates whether to signal an error interrupt.

1: An error interrupt request exists.

0: No error interrupt request exists.

DONEINT

Normal Transfer

Complete

Interrupt Status

Normal Transfer Complete Interrupt Status (Initial value: 0, R)

Indicates whether a Normal Transfer Complete Interrupt is signaled.

This bit becomes “1” when either the Normal Chain Complete bit (NCCMP) is set and

the Normal Chain Complete Interrupt Enable bit (NCCMPIE) is set, or when the

Normal Transfer Complete bit (NCCMP) is set and the Normal Transfer Complete

Interrupt Enable bit (NDCMPIE) is set.

1: A Normal Transfer Complete Interrupt request exists.

0: No Normal Transfer Complete Interrupt request exists.

CHNEN

Chain Enable

Chain Enable (Initial value: 0, R)

This bit is a copy of the Chain Enable bit in the PDMAC Control Register.

XFRACT

Transfer Active

Transfer Active (Initial value: 0, R)

This bit is a copy of the Transfer Active bit in the PDMAC Control Register.

9ACCMP

Abnormal Chain

Completion

Abnormal Chain Complete (Initial value: 0, R)

1: Indicates that the Chain transfer ended in an error state. In other words, this

reflects an OR operation of the PDMAC Status Register bits [4:0].

0: Indicates that no error has occurred in the Chain transfer since the previous error

bit was cleared.

Note: Bits [4:0] of the PDMAC Status Register must be cleared in order to clear this

bit.

NCCMP

Normal Chain

Completion

Normal Chain Complete (Initial value: 0, R/W1C)

1: Indicates that the Chain transfer ended in the Normal state.

0: Indicates that Chain transfer has not ended since this bit was previously cleared.

7NTCMP

Normal Data

Transfer

Complete

Normal Data Transfer Complete (Initial value: 0, R/W1C)

1: Indicates that the data transfer specified by the PDMAC Register ended in the

Normal state.

0: Indicates that data transfer has not ended since this bit was previously cleared.

Figure 10.4.66 PDMAC Status Register (1/2)

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