TMPR4925 datasheet(356/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-94

Bits

Mnemonic

Field Name

Description

CHNEN

Chain Enable

Chain Enable (Initial value: 0) (Read Only)

When the current data transfer is complete, this field reads the next data command

Descriptor from the address indicated by the PDMAC Chain Address Register then

indicates whether to continue the transfer or not.

This bit is only set to “1” when either a CPU Write process or a Descriptor Read

process sets a value other than “0” in the PDMAC Chain Address Register.

This bit is cleared to “0” if either the Channel Reset bit is set, or “0” is set in the

PDMAC Chain Address Register by a CPU Write or a Descriptor Read process.

1: Reads the next data command Descriptor.

0: Does not read the next data command Descriptor.

XFRACT

Transfer Active

Transfer Active (Initial value: 0, R/W)

Specifies whether to perform DMA transfer or not.

Setting this bit after setting the appropriate value in the register group initiates DMA

data transfer.

This bit is not set if the PDMAC Count Register value is “0” and the Chain Enable bit

is cleared when “1” is written to this bit.

Even when a value other than “0” is written to the Chain Address Register, “1” is set to

this bit and DMA transfer automatically starts.

Data transfer will be stopped after a short delay if this bit is cleared while the data

transfer is in progress.

This bit is automatically cleared to “0” either when data transfer ends normally or is

stopped by an error.

1: Perform data transfer.

0: Do not perform data transfer.

5:4



Reserved



3:2

XFRMODE

Transfer Mode

Transfer Size (Initial value: 0, R/W)

Specifies the transfer type (see detailed description in 10.3.9.4).

00: 1 DWORD (32-bit) with no overlap of G-Bus and PCI operation.

01: up to 16 DWORDs with no overlap of G-Bus and PCI operation.

10: Reserved

11: Reserved

XFRDIRC

Transfer Direction Transfer Direction (Initial value: 0, R/W)

Specifies the DMA data transfer direction.

1: Transfers data from the G-Bus to the PCI Bus.

0: Transfers data from the PCI Bus to the G-Bus.

CHRST

Channel Reset

Channel Reset (Initial value: 1, R/W)

Resets the DMA channel.

This bit must be cleared by the software in advance so the channel can start the data

transfer.

1: All logic and State Machines are reset.

0: The channel becomes valid.

Figure 10.4.65 PDMAC Configuration Register (2/2)

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