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CYT4DNJBJS bảng dữ liệu(PDF) 161 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 161 Page - Infineon Technologies AG |
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161 / 209 page ![]() Datasheet 161 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications 26.11 Ethernet specifications Table 26-31 Ethernet specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions Ethernet General Specifications SID364C CL Load capacitance – – 25 pF for all between MAC and PHY for MII-IF, RMII-IF, MDC/MDIO-IF SID364A CL Load capacitance – – 10 pF for all between MAC and PHY for RGMII-IF SID368 fSYS System clock max frequency – – 100 MHz Guaranteed by design SID369 fAXI AXI clock max frequency – – 200 MHz Guaranteed by design Ethernet MII Specifications Recommended I/O configuration: HSIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1 SID370 tTXCYC MII tx_clk cycle 39.5 40 40.5 ns SID371 tRXCYC MII rx_clk cycle 39.5 40 40.5 ns SID372B tSKEWT MII Transmit data (txd,tx_en,tx_er) valid after tx_clk 0– 25 ns SID373 tSUR MII Receive data setup to rx_clk rising edge 10 – – ns SID374 tHOLDR MII Receive data hold to rx_clk rising edge 10 – – ns SID375 fTXRX_CLK MII TX/RX_CLK Clock frequency –50ppm 25 +50ppm MHz SID376B DUTY_TX- RX_CLK TX/RX_CLK Duty cycle 35 – 65 % SID365A tRF Input rise / fall time – – 2 ns 20% to 80% SID365E_1 tRFO Output rise / fall time – – 6.5 ns 20% to 80% Ethernet RMII Specifications Recommended I/O configuration: HSIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1 SID375A fREF_CLK RMII reference clock frequency (input) –50ppm 50 +50ppm MHz SID375B fREF_- CLK_OUT RMII reference clock frequency (output) –2% 50 +2% MHz SID376C DUTY_REF Duty cycle of reference clock (output) 35 – 65 % SID377 tSU RXD[1:0], CRS_DV, RX_ER Data Setup to REF_CLK rising edge. 4–– ns SID378 tHOLD RXD[1:0], CRS_DV, RX_ER, Data hold from REF_CLK rising edge 2–– ns SID379 tTXOUT TXD[1:0], TX_EN Data output delay from REF_CLK rising edge 2– 14 ns SID365C tRF Input rise / fall time – – 2 ns 20% to 80% |
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