CYT4DNJBJS datasheet(158/209 Pages) INFINEON

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Datasheet

158

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID348A fPFD_S

Phase Detector

Frequency, clock output

of the Reference Divider

(Q) and Feedback Divider

(P)

3.988

–

20.003 MHz Fractional operation OFF

SID349A fPFD_F

Phase Detector

Frequency, clock output

of the Reference Divider

(Q) and Feedback Divider

(P)

7.9988

–

20.003 MHz Fractional operation ON

SID345A fVCO

VCO frequency,

Clock output of 'Voltage

Control Oscillator (VCO)'

399.94

–

800.12 MHz

SID342D1 PLL400_LJIT1 Long term jitter

–0.25

–

0.25

For 125 ns

Guaranteed by Design

fVCO: 800 MHz

(Integer mode)

fIN: ECO

fPFD: 4 MHz

fOUT: 100 MHz to 400 MHz

SID343D1 PLL400_LJIT2 Long term jitter

–0.5

–

0.5

For 500 ns

Guaranteed by Design

fVCO: 800 MHz

(Integer mode)

fIN: ECO

fPFD: 4 MHz

fOUT: 100 MHz to 400 MHz

SID344D1 PLL400_LJIT3 Long term jitter

–1

–

For 1000 ns

Guaranteed by Design

fVCO: 800 MHz

(Integer mode)

fIN: ECO

fPFD: 4 MHz

fOUT: 100 MHz to 400 MHz

SID345E1 PLL400_LJIT5 Long term jitter

–1.5

–

1.5

For 10000 ns

Guaranteed by Design

fVCO: 800 MHz

(Integer mode)

fIN: ECO

fPFD: 4 MHz

fOUT: 100 MHz to 400 MHz

Table 26-26

FLL specifications

Spec ID

Parameter

Description

Min

Typ

Max Units

Details/conditions

SID350

tFLL_WAKE

FLL wake up time

–

µs

Wakeup with < 10 °C

temperature change

while in DeepSleep.

fFLL_IN = 8 MHz,

fFLL_OUT = 100 MHz,

Time from stable

reference clock until FLL

frequency is within 5% of

final value

SID351

fFLL_OUT

Output frequency from

FLL block

–

100

MHz Output range of FLL

divided-by-2 output

Table 26-25

PLL specifications (continued)

Spec ID

Parameter

Description

Min

Typ

Max Units

Details/conditions

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