LPC86X datasheet(67/99 Pages) NXP

67 / 99 page

LPC86x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev.3 — 28 April 2023

67 of 97

NXP Semiconductors

LPC86x

32-bit Arm Cortex-M0+ microcontroller

12.7 SPI interfaces

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by an external device and PCB, the maximum supported bit rate for SPI

master mode is 30 Mbit/s, and the maximum supported bit rate for SPI target mode is 1/(2

x 26 ns) = 19 Mbit/s at 3.0v

 VDD  3.6v and 1/(2 x 42 ns) = 12 Mbit/s at 1.8v  VDD <

3.0v.

Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for

all digital pins except the open-drain pins PIO0_10 and PIO0_11.

Table 26.

SPI dynamic characteristics

Tamb = 40 C to 105 C; CL = 20 pF; input slew = 1 ns. Simulated parameters sampled at the 30 %

and 70 % level of the rising or falling edge; values guaranteed by design. Delays introduced by the

external trace or external device are not considered.

Symbol

Parameter

Conditions

Min

Max

Unit

SPI controller

tDS

data set-up time

1.8 V <= VDD <= 3.6 V

tDH

data hold time

1.8 V <= VDD <= 3.6 V

tv(Q)

data output valid time

1.8 V <= VDD <= 3.6 V

SPI target

tDS

data set-up time

1.8 V <= VDD <= 3.6 V

tDH

data hold time

1.8 V <= VDD <= 3.6 V

tv(Q)

data output valid time

3.0 V <= VDD <= 3.6 V

1.8 V <= VDD < 3.0 V

LPC86X bảng dữ liệu(PDF) 67 Page - NXP Semiconductors

LPC86X bảng dữ liệu(HTML) 67 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

bảng dữ liệu tải về

Link URL